D S D CO -2 Topics
2.1 Verilog Construction Modeling Styles HDL coding/
2.1 Adders and subtractors – Half, Full and 4-bit Parallel - Verilog
code
2.1 Decoders- Single Gate Decoders, Multiple-output decoders,
Seven segment decoders
2.1 Encoders- No input Priority encoder, Input Priority encoder,
BCD priority encoder
2.1 Decoders and Encoders - Verilog Code
2.2 Multiplexers- 2-to-1; 4-to-1; 4-to-1 4-bit bus; - Verilog Code
2.2 De-multiplexers- 4-bit decoder/demultiplexer; - Verilog
Code
2.2 Logic circuits construction with decoders and multiplexers
2.2 Magnitude comparator- 2-bit; 4-bit; Verification with HDL
2.2 Verilog code for Boolean equations
2.2 Development of parity generators and checkers HDL coding with
Simulation/Group Discussion
2.2 Verilog code for gate level circuits
-------------------------------------------All The Best For Your Exams-------------------------------------------
2.1 Adders and subtractors – Half, Full and 4-bit Parallel - Verilog
code
2.1 Decoders- Single Gate Decoders, Multiple-output decoders,
Seven segment decoders
2.1 Encoders- No input Priority encoder, Input Priority encoder,
BCD priority encoder
2.1 Decoders and Encoders - Verilog Code
2.2 Multiplexers- 2-to-1; 4-to-1; 4-to-1 4-bit bus; - Verilog Code
2.2 De-multiplexers- 4-bit decoder/demultiplexer; - Verilog
Code
2.2 Logic circuits construction with decoders and multiplexers
2.2 Magnitude comparator- 2-bit; 4-bit; Verification with HDL
2.2 Verilog code for Boolean equations
2.2 Development of parity generators and checkers HDL coding with
Simulation/Group Discussion
2.2 Verilog code for gate level circuits
-------------------------------------------All The Best For Your Exams-------------------------------------------
